This invention relates to non-volatile semiconductor memory devices having a floating gate that is capable of being electrically charged and electrically discharged, and more particularly, to such a memory device having a multilayer system of conductors comprised of two polysilicon layers, portions of which are connected to each other, and at least one metal layer.
An array of such memory devices is sometimes known as an EEPROM or an E.sup.2 PROM (electrically erasable programable read only memory). The memory device is based on an insulated gate field effect transistor (IGFET) having a floating gate and a control gate. The control gate is typically positioned over and spaced from the floating gate and may have the dual functions of "conditioning" the transistor for "reading" by connection to signals from the "word select" line and at other times conditioning the transistor for being erased, responding to other "word select" line signals.
An especially effective device feature for charging the floating gate (writing) includes a textured "charging" electrode having a capacitive relationship with an extended portion of the floating gate. The surface of the charging electrode facing the floating gate is rough or textured. When a large negative voltage (e.g., 20 volts) is applied to the charging electrode relative to the adjacent floating gate, the latter acquires electrons by tunneling from the textured-surface of the charging electrode. The floating-gate under-surface is usually smooth. The textured and smooth surfaces advantageously provide unidirectional electron emission from the textured charging electrode to the floating gate. It is thought that this is attributable to Fowler-Nordheim tunneling at high field points at peaks in the textured surface.
In a similar manner, for discharging the floating gate and erasing the memory, the adjacent surfaces of the floating gate and the control gate are, respectively, textured and smooth so that for a large negative voltage (e.g., 20 volts) applied to the floating gate relative to the control gate, electrons are conducted away from the control gate by tunneling.
A detailed portion of the prior art memory device structure that is used to implement these programing and erasing functions is illustrated in FIG. 1. On the top surface of semiconductor silicon substrate 10 an insulative layer of silicon dioxide 11 is grown. A first polysilicon layer 12 is deposited in a lower plane 17 over the oxide layer 11 and the top surface is textured by process steps described later herein. Another silicon dioxide layer 13a is grown over the textured top surface of the first polysilicon layer and at the same time more oxide 13b is grown over the uncovered surface of the substrate 10.
A second polysilicon layer 14 is deposited partly in lower plane 17 and partly in an upper plane 18 above the first polysilicon layer 12. Its top surface is then textrued. A silicon dioxide layer 15 is grown over the top textured surface of the second polysilicon layer 14.
A third polysilicon layer 16 is deposited in upper plane 18 over a portion of the second polysilicon layer 14.
The second polysilicon layer 14 serves as the floating gate. Its lower (right hand portion as shown) being spaced from the channel region (not delineated in FIG. 1) by silicon dioxide layer 13b. The first polysilicon layer 12 is the afore-mentioned charging electrode from which the floating gate 14 received charge at programing. The third polysilicon layer 16 is the aforementioned control gate by which, among other functions, stored charge on the floating gate is removed.
Although such prior art devices exhibit many excellent performance characteristics, especially for use in an array, the inevitable stacking and crossing over of the three polysilicon layers and associated insulation layers produces sharp changes in the surface. Since at least one additional conductor, namely a low resistance metal "bit line", is needed, that bit line must be deposited over the irregular surface formed by the three polysilicon layers. Regions of incomplete conductor deposition occur at the sharp changes in the surface leading to opens or potential opens which at least degrade the reliability of the array.
It is an object of this invention to provide a non-volatile memory device retaining the advantages and overcoming the shortcomings of the above-mentioned prior art devices.
It is a further object of this invention to provide such a memory device requiring only one polysilicon layer having a textured surface.
It is yet a further object of this invention to provide such a device wherein the silicon dioxide layer through which tunneling is effected to charge the floating gate is the same layer through which it may be discharged.
It is even a further object of this invention to reduce the number of conductor layers needed for forming an array of such memory devices.